-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
-- Date        : Sat Aug  1 20:11:24 2020
-- Host        : USER-King running 64-bit Service Pack 1  (build 7601)
-- Command     : write_vhdl -force -mode funcsim
--               E:/Xilinx/Bird/Bird.srcs/sources_1/ip/PICTURE_R_ROM/PICTURE_R_ROM_sim_netlist.vhdl
-- Design      : PICTURE_R_ROM
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7s15ftgb196-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_bindec is
  port (
    ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ena : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_bindec : entity is "bindec";
end PICTURE_R_ROM_bindec;

architecture STRUCTURE of PICTURE_R_ROM_bindec is
begin
\ENOUT_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => addra(1),
      I1 => addra(0),
      I2 => addra(2),
      I3 => ena,
      O => ena_array(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_mux is
  port (
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
    clka : in STD_LOGIC;
    DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \douta[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \douta[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end PICTURE_R_ROM_blk_mem_gen_mux;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_mux is
  signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(0),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(0),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(0),
      O => douta(0)
    );
\douta[1]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(1),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(1),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(1),
      O => douta(1)
    );
\douta[2]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(2),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(2),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(2),
      O => douta(2)
    );
\douta[3]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(3),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(3),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(3),
      O => douta(3)
    );
\douta[4]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(4),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(4),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(4),
      O => douta(4)
    );
\douta[5]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(5),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(5),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(5),
      O => douta(5)
    );
\douta[6]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(6),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(6),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(6),
      O => douta(6)
    );
\douta[7]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => sel_pipe_d1(0),
      I1 => DOADO(7),
      I2 => sel_pipe_d1(2),
      I3 => \douta[7]\(7),
      I4 => sel_pipe_d1(1),
      I5 => \douta[7]_0\(7),
      O => douta(7)
    );
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => ena,
      D => sel_pipe(0),
      Q => sel_pipe_d1(0),
      R => '0'
    );
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => ena,
      D => sel_pipe(1),
      Q => sel_pipe_d1(1),
      R => '0'
    );
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => ena,
      D => sel_pipe(2),
      Q => sel_pipe_d1(2),
      R => '0'
    );
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => ena,
      D => addra(0),
      Q => sel_pipe(0),
      R => '0'
    );
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => ena,
      D => addra(1),
      Q => sel_pipe(1),
      R => '0'
    );
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => ena,
      D => addra(2),
      Q => sel_pipe(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init is
  port (
    \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init is
  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 0,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_01 => X"FFFFFFFFFFFFFFFEFBF7F2EDE8E4E1E0E3E9EFF7FDFFFFFFFFFFFFFFFFFFFFFF",
      INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_04 => X"FFFFFFFEFBF7F2EDE8E4E1E0E3E9EFF7FDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_07 => X"FAF5F0E8E0D7D2D0D2D9E2EDF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
      INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_0A => X"D8CCC5C1C2C8D3E2F1FDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFAF5EEE5",
      INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_0D => X"BABCC4D2E4F3FBFDFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFAF5EEE3D4C7BFBB",
      INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_10 => X"CCDCE6EDF1F7FBFDFDFDFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF9F5EDE0D0C4BEBEBCBAB9BF",
      INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_13 => X"D6DBE1E8F1FAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF8F3EBDBCBC1C0C4C9C7C1BFC2C7CDD2",
      INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_16 => X"E0F3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFDF8F2E8D7C6BDC0CAD4D7D1CAC5C4C6C7C7C7C9D2",
      INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_19 => X"FFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_1A => X"FFFFFFFFFFFFFFFDF9F4EAD8C4BBBDC8D7DEDBD1C7C4C3C2BEB8B4B9C7DCF3FD",
      INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_1D => X"FFFFFFFEFBF8F0DDC7BAB8C0CBD0CAC0B6B2B3B5B3AEADB0B6C3D4E2EBF3FDFF",
      INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_20 => X"FEFEF8E6CEBBB3B3B6B4A8998E8D9199A1A9B3BDC4CAD0D6E0EDFCFFFFFFFFFF",
      INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
      INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_23 => X"D5BDADA39C9686756A696E778599B0C7DCE6E6DFDCE4F3FFFFFFFEFFFFFFFFFF",
      INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFF0",
      INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_26 => X"858075685F5C5859627694B8D8EFF6ECE2DEE4EEF5F9FCFFFFFFFFFFFFFFFFFF",
      INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFADEC1A995",
      INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_29 => X"706553423C466186ADD0E7EEEBE7E7EAEEF3FAFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5C8AB94807B7A76",
      INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2C => X"1D192B4A719ABFD9E9F3F8F6F1F1F6FEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEACEB197837F878E8B795936",
      INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2F => X"39608BB1D3EDFFFFF7EFF0F7FCFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEED5B89C898998A6A791683811000419",
      INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_32 => X"A6C8E5F5F6F2F0F3F6F9FCFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFF0D9BEA28E8EA1B4B9A7804D2106000518355A80",
      INIT_34 => X"FFFFFFFFFFFFFFFFFDFBF8F6F2EEECEAE9E9EBEEF1F4F6F6F8F9FBFCFDFEFFFF",
      INIT_35 => X"E3F0F7FCFBF9FAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_36 => X"FFFFFFFFFFFFFFFFF2DDC4AA9594A4BAC4B99A6E442310080B18304B6B8DB0CF",
      INIT_37 => X"FFFFFFFEFBF6F1EBE2DAD3CECBCBD0D7DFE6EAECEEF2F6FAFBFEFFFFFFFFFFFF",
      INIT_38 => X"FFFBF9FCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_39 => X"FFFFFFFFF3E3CFB7A09BA7BAC9C6B2916C4B2F190B070E1D3350759CC0DEF6FF",
      INIT_3A => X"F7EFE5DACCC1B8B2AEAEB4BCC7D1D6D9DDE4ECF3F8FCFFFFFFFFFFFFFFFFFFFF",
      INIT_3B => X"FAFCFDFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
      INIT_3C => X"F7EDDFCCB3A5A8B8C6CCC2AB8D6C4C2E150400000C23446D97BDDFF8FDF9F6F7",
      INIT_3D => X"B2A9A5A3A2A1A5A9AFB6BABDC2CCDAE7F1FAFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF0E1D1C1",
      INIT_3F => X"C3ADA9B1C0CAC8B8A184644529120200000D27496F95B9DAEDF3F5F7F7F8F9FC",
      INIT_40 => X"B0B1AFADABA9A8A9ADB9CBDCEBF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFAF5EDDD",
      INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDE9D3BEABA0A1A6AC",
      INIT_42 => X"B4C1C5BDAC957A5E422914070309192F4B698AAFCCE2F0F7F7F2F3F9FFFFFFFF",
      INIT_43 => X"BBB3AEA9ABB5C7DAEBF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFCFDFAEDD1B5A9A9",
      INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCE4C9AF9B97A2B1BFC8CAC9C3",
      INIT_45 => X"B5A48C71543820120B0C131E2C3F597CA0C0DBEEF2EEEBF1FCFFFFFFFFFFFFFF",
      INIT_46 => X"B9C1D0E0EEF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE3C2ACA3A5B3BDBD",
      INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFEFFFFFCECD5BAA19196A7B8C7D3D9DAD5CDC5BDB9",
      INIT_48 => X"54382218171B1F2021263653789EC2DCECEDEAEAEEF3F7FAFEFFFFFFFFFFFFFF",
      INIT_49 => X"F2FAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D6B8A49AA0AEB6B5A89174",
      INIT_4A => X"FFFFFFFFFFFFFEF6EFE8DED0BDA994858696A9BCCAD2D3D0CBC9C9C9CCD3DEE9",
      INIT_4B => X"27323731251D2036587EA6C8E3F1F5F1EBE7E8F0FDFFFFFFFFFFFFFFFFFFFFFF",
      INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9DDC0A6938E9DA9ACA38B6B4A2E1E1E",
      INIT_4D => X"FFFFFCEDDDD0C6BAAA9B8D83808593A3B2BBBFC1C4CAD1D7DEE6EFF4F8FCFFFF",
      INIT_4E => X"2B1912203A5C82A8CCEAFBFEF1E0DAE4FBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_4F => X"FEFEFFFFFFFFFFFFFFFFFFFFFBE2C6A9918792A2AAA2896743271A213243493F",
      INIT_50 => X"C9BDB6AEA19692938F89878B96A2ABB6C3D2DFE9F2F9FFFFFFFFFFFFFEFEFDFD",
      INIT_51 => X"233B5A7EA6CEEDFBF3DBC9CADCF3FDFEFDFFFFFFFFFFFFFFFFFFFEFEFFFCF0DC",
      INIT_52 => X"E5E9EDF0F4FAFEFCEFD9C0A7938D9AAEB7B0956F4828171C2B3B403523110912",
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      INIT_54 => X"82ADD2EAECDAC5BBC2D6E6F1F9FFFFFFFFFFFFFFFFFFFDF7F0E7D8C7B9B2B0AB",
      INIT_55 => X"D8DDDFDCD1BFAEA19AA0B3C6CFC5A77D50280F0B121C201A110A0A121B283C5A",
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      INIT_57 => X"DCD7C8BBBCCBDCECF8FFFFFFFFFFFFFFFFFFFDF0E3D4C4B7AEAAA9A8ABB5C4D2",
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      INIT_5A => X"C5D1DEEBF7FFFFFFFFFFFFFFFFFFFCECDAC8B9ADA8A8ACB4C0D0E0EDF1EADED1",
      INIT_5B => X"A6BBD3E6EEE4CAA47A502D1A110E0B0C141E27292015101B385C82A6C1CAC8C3",
      INIT_5C => X"FDFFFFFFFFFFFFFFFFFFFAEFE2D2BCA1887365636D7E8F9B9B938A827F828995",
      INIT_5D => X"F2FFFFFFFFFFFFFFFEFEFBE9D6C4B5ACA9AFBBCADAE9F4FCFFFFF9F1EDEEF3F8",
      INIT_5E => X"EFEDDDC4A5846753463D332D3034352C1B09000117365A7FA1B8C6CDD4DADEE5",
      INIT_5F => X"FFFFFFFFFFFFFCF6F0E6D5BEA791807D87939EA7A3978A817D808895A4B8CFE3",
      INIT_60 => X"FFFFFFFFF4F4F1DFCDBEB3AEB2BFD0E1EEF6FAFDFFFFFFFEFDFDFDFEFFFFFFFF",
      INIT_61 => X"CDB9A495887B6A5C544D44331E0B00000D223E5F83A4C0D3DDDDD8DAE8FCFFFF",
      INIT_62 => X"FFFFFEFEFDFAEFDEC9B3A199A3B1BEC4C1B7A99D979292959DACC0D5E4EBE8DD",
      INIT_63 => X"E7E7E4D3C4B8B3B6BFD0E2F2FCFFFFFEFFFFFFFFFEFEFEFFFFFFFFFFFFFFFFFF",
      INIT_64 => X"BFB29F8E7F7260472D16060004112541668FB5D2E0DCD0CCD7EDFBFFFEFEFFFF",
      INIT_65 => X"FFFFFEF2E3D1C1B7BAC3CED6D8D4CCC2B6AA9D938F95A3B5C7D5DDE0DFDAD2CA",
      INIT_66 => X"BBB4B4BDCBDDEFFEFFFFFFFFFFFFFFFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_67 => X"B0A39279614B37281E1A1D2C49729FC5DADACCC2C5D5E5EFF4FBFCFCD7D7D5C6",
      INIT_68 => X"ECE0D4C9C4C5C8CBD2DADEDCD1BBA1887670758292A3B3C0CBD4DADBD8D1C6BA",
      INIT_69 => X"CFE2F3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7",
      INIT_6A => X"A18D786148332523345784ADC8CFC8BDBCC6D4DFEAF4F7F7CDCDCABEB6B3B5BF",
      INIT_6B => X"CBC0B7B3BACADBE2D8BD99745645424A5868798A9BADBFCBD2D5D7D8D7D2C7B4",
      INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAF4EEE4D8",
      INIT_6D => X"79583C2D314B7299B5C3C3BFBCC1CAD5E0EEF1F1CCCCC9BFB7B3B6C0D0E2F3FF",
      INIT_6E => X"A0B4CDDDD8BC946841281D1D25313F50647B95A8B7C5D4E1EBEEECE3D8C9B59A",
      INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFAEBD9C4AE9E",
      INIT_70 => X"48587595AEBCC2C2C1C2C6CDD7E6E9E9CECECCC1B9B4B7C0CFE2F3FFFFFFFFFF",
      INIT_71 => X"D9C39F734928140806091221364F6B8092A4B9CDDCE5EAECEBE6D9C4A582624D",
      INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEFEFCFBFAFAFEFFFFFFFAE8CFB49A92A4BFD6",
      INIT_73 => X"B2BDC5CACAC9C8CAD0DEE1E1CCCCC9BEB5B1B3BDCCE0F3FFFFFFFFFFFFFFFFFF",
      INIT_74 => X"704D30190900000A1B304553606E8193A0ABB6C2CED5D6D0C0A9927F798191A3",
      INIT_75 => X"FFFFFFFFFFFFFFFFFFFEFAF5EFEAE9EEF8FFFFFBF0DFC6AA989DB3CCD9D2B996",
      INIT_76 => X"D2D0CCCBCFD9DDDDC6C6C4B8B1ADB0BACADFF1FFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_77 => X"180100010F1E282E3239444F58616F8499ACBDC9CCC7BEB5B3B4B7BBBEC4CBD0",
      INIT_78 => X"FFFFFFFFFFFDF6ECE1D8D5DBE9F7FFFEFAF0DFC2A69DA9C0D6DFD6C1A4815C37",
      INIT_79 => X"D0DADDDDC0C0BDB1A9A6AAB6C7DCF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_7A => X"1820211E1C1C2025282F3D546D859EB7CBD7DDDFE2DFD9D1CBCACCD0D2CFCCCC",
      INIT_7B => X"FFFCF1E3D2C4BDC0CDDCE7EBECEAE0CAAEA0A3B5CEE2E8E1CEB18B613A1B0E0F",
      INIT_7C => X"BDBDB9ABA19EA1AEC1D9F0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_7D => X"34343536373B445565768AA2BBCFDEEAF3F2EBE1D6D0CCC9C6C4C5CAD2DEE1E1",
      INIT_7E => X"C8B3A29EA6B1BCC0C3C3C1B6AAA1A1ACBFD6E3E7DFCBAC87644738363A3D3A37",
      INIT_7F => X"978E919FB7D1EAFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6E0",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 3) => addra(11 downto 0),
      ADDRARDADDR(2 downto 0) => B"111",
      ADDRBWRADDR(15 downto 0) => B"0000000000000000",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
      DIADI(31 downto 8) => B"000000000000000000000000",
      DIADI(7 downto 0) => dina(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 0) => B"0000",
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
      DOADO(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7 downto 0),
      DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
      DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
      DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
      DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
      ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
      ENBWREN => '0',
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => ena,
      REGCEB => '0',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
      WEA(3) => wea(0),
      WEA(2) => wea(0),
      WEA(1) => wea(0),
      WEA(0) => wea(0),
      WEBWE(7 downto 0) => B"00000000"
    );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => ena,
      I1 => addra(12),
      I2 => addra(13),
      O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\ is
  port (
    \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\;

architecture STRUCTURE of \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\ is
  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 0,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"7271727576777D899DB2C6D9E7EFF0EBE2D6CABDB5B4BCC8D6E4E8E8BFBFBBA7",
      INIT_01 => X"838B949CA3A9ADAEACA9A6A6AEC0CFD9DCD3C0A8917D716D6D6E6C6D6E707272",
      INIT_02 => X"ABCAE5F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6DEC2A68F83",
      INIT_03 => X"897C72737E91A8BED2E0E9EBE5D7C5B5ACB1BFCFDFEEF2F2C6C6C1A68E7F7F8F",
      INIT_04 => X"99ABBAC4C6BEB1A4A2A9B5C1C9C9C4BBB2A9A39E9C9B9CA1A7ACAEAEACA8A197",
      INIT_05 => X"FAFDFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6DBBC9D806D696D7887",
      INIT_06 => X"718298AFC3D2DCE0DCD2C4BAB8C3D2E0EDF8FAFAD5D5CFAF917C7888A3C2DDF0",
      INIT_07 => X"DED0BCA99F9EA3ABB2B5B6B6B5B4B1AEABAAABB0B5BABAB8B4AEA49785756967",
      INIT_08 => X"FCFEFEFDFBFBFAF9F8F7F6F4F3F1F0F3F4F0DEC6AB9079696469758AA4BDD1DE",
      INIT_09 => X"BECBD2D5D4D2D0CFD2DDE8F0F6FDFEFEE8E8E3C4A68D828BA0B9D0E1ECF2F5F8",
      INIT_0A => X"A9A19C99979596999B9C9C9B9A9898999A99969089817A726963616774869AAD",
      INIT_0B => X"F4F2EEEAE7E3E1DFDCD7D3D0CDC7BAAC9D8F827974757B899FB4C6D3D6D0C3B5",
      INIT_0C => X"D3DAE0E5EAF1F8FBFCFEFEFEF5F5F1DBC5B0A4A2ABB7C4CFD8DFE4E9EEF2F4F4",
      INIT_0D => X"7C726E6F71727375767673706C6660584F4946494E5662718393A2AFBBC4C9CD",
      INIT_0E => X"D1CDC9C6C4BFBAB7B4AFA9A4A09C979088817F848F9CA9B5BDC3C4C0B8AA9A8A",
      INIT_0F => X"FBFFFFFFFFFFFFFFFBFBF9ECDFD2C6BDB9BABCBFC3C9CFD5DBE0E5E8E8E4DED7",
      INIT_10 => X"4645474C5255534E48403A332C292C38475A6E82929DA2A6AEB7C1CCDBE9F2F7",
      INIT_11 => X"B6B5B5B5B3B1B1B3B4B5B3ACA399908D8D8F959DA9B8C5CBC6B49C8269564C47",
      INIT_12 => X"FFFFFFFFFFFFFDF7F1E8DED1C6BDB7B1AFB1B5BBC0C5CBD0D1CEC8C3BEBBB9B8",
      INIT_13 => X"333C3F3D39363536363941516377899CA4A6A5A6AFBBC9D9E9F6FCFDFEFFFFFF",
      INIT_14 => X"CBCBCBCDCECDCBC5BFB7AEA69F989597A0B2C4CFCBB89F816349372B241F2129",
      INIT_15 => X"FFFFFEFBF8F3EBDED1C4B9ACA39E9E9FA1A6ADB4B9BAB9B8BABEC0C2C3C5C9CA",
      INIT_16 => X"3A3D45505A63708192A0ACB4B6B4B3B7C3D1DDE7F2FBFFFFFEFFFFFFFFFFFFFF",
      INIT_17 => X"D8D8D7D6D6D4D0C7B9ACA09A9FB0C2CECBBBA58A6B4B301B0C02020C1B2A3438",
      INIT_18 => X"FDFAF3E8DDD1C6B7A89A9089878D98A3ACB3B9BEC4CBCFD0D1D2D4D5D6D6D6D7",
      INIT_19 => X"8594A2B3BFC9CCCAC7C4C8D3E5F0F5F7FAFEFFFFFFFFFFFFFFFFFFFFFFFFFFFD",
      INIT_1A => X"E6EAEAE1D2BFAEA2A3B0C0CBC8BBAA937656391F0B0000071729384149526274",
      INIT_1B => X"EDE4D9C8B49F8B7D79808E9FAFBBC4CCD3DADDDDDCDCDCDCDBDADADBDBDCDEE1",
      INIT_1C => X"DDE4E4E0DBDCE4F3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCF4",
      INIT_1D => X"E0CDBAACA9B2BFC7C4BAAD9B8264472C180D0E1A2D4256626C77889AAAB8C4D3",
      INIT_1E => X"B8A18D818796A5B5C5D1D8DBDEE2E3E3E1E0DFDFDEDEDEDFE0E1E4E9F0F6F7EF",
      INIT_1F => X"EBECF0F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF5EEE2CF",
      INIT_20 => X"B3B8BFC3BEB4A99A88725C4A3D393F4C5E7387959FA9B6C2CAD0D6DEE8EEEFEE",
      INIT_21 => X"A1B2C1CEDAE2E3E2DFDFDEDDDCDBDAD9D9D9D9DBDCDEE1E5EAEFEFE9DED0C2B7",
      INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAF4EBDDC8B2A19694",
      INIT_23 => X"B8AFA59B8F83786F6C6F788594A6B7C3CBD2D7DBDAD8D8DEE7EFF4F6F8FAFCFD",
      INIT_24 => X"E8EBE7E1DAD6D4D3D3D2D1D0D0D1D1D3D4D6D8DADDDFDFDCD6CFC7C0BCBDBFBE",
      INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8ECDECBB6A69FA1ABBECED9E2",
      INIT_26 => X"9A979595989FA8B2BCC7D1D8DCDDDBD9D4D1D4DCE8F1F9FFFFFFFFFFFFFFFFFF",
      INIT_27 => X"D7D2CFCECECDCCCCCDCECECFD0D1D2D3D3D4D3D1CFCCC9C5C1BEBCB9B2ABA59F",
      INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4E4CFB9A69FA4B1C2D6E3EAEDEFEDE7DF",
      INIT_29 => X"B6BABDBFC0C0BFBFBEBDBDBEC1C7D1DEEAF3F9FFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2A => X"D7D7D8D9DBDBDAD8D5D3D0CFD0D1D1CFCDCAC6C1BCB8B4B1ADAAA8A8A8ABAEB2",
      INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFAE8D5C0AEA4A6B2C2D2E2EBEDEDECEBE7E2DDDAD8D7",
      INIT_2C => X"ACA197949396A0ACBBC9D9E9F3F8FBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2D => X"EDEDEAE4DDD5D0CED0D3D4D2CCC6BFB7B2AEACABABACAEB1B4B8BDC1C3C0BBB5",
      INIT_2E => X"FFFFFEFEFFFCF0DCC9B9B0B0B9C5D1DBE4E6E4E1E0E1E2E4E5E5E5E5E4E5E7EA",
      INIT_2F => X"778398B0C8DCECFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_30 => X"DFD6D0CED1D6D8D4CCC3B9B0AAA7A7A9ACAFB4B8BDC1C6CAC9C1B6AA9B887873",
      INIT_31 => X"F7F0E1CEC0BBBFCAD5DBDCDCDDDAD5D1D0D3D8DDE2E5E5E4E2E3E6EBEFF1EEE7",
      INIT_32 => X"CDE4F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFB",
      INIT_33 => X"D4D8D9D5CEC5BBB2ADABABADB0B3B7BCC0C4C9CCCBC4B9AEA08C7A72747F95B2",
      INIT_34 => X"BDC6D6E6EEEBE1D8D2CCC8C5C3C5C9CED1D0CBC5BFBDC0C6CDD4D7D6D4D1CFD0",
      INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF4EBDECEBF",
      INIT_36 => X"D0CAC3BCB8B6B6B7B7B7B8B9BABBBEC0C0BDBAB8B2A695877E7E8DA8C6E0F6FF",
      INIT_37 => X"F8ECDACAC0BDBCBCBBBABCBCB9B0A2938680818893A0ADB8C1C8D0D6DADBD9D6",
      INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF2E4D3C1B7BED1E7F7",
      INIT_39 => X"C5C4C3C2BFBCB8B5B3B1B1B2B4B6BCC2C6C4B8A8978C91A8C5E0F6FFFFFFFFFF",
      INIT_3A => X"B0AFB2B5B4B0ACA79C8A76615046464C5A6C8398ABBDCEDADDDCD9D6D4D0CCC8",
      INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCEFDECAB8B3C0D8EFFCF8E6D0BB",
      INIT_3C => X"C8C2BDB7B3B0AFAFB2B7C1CCD6DAD5C8B8A7A5B3CAE2F6FFFFFFFFFFFFFFFFFF",
      INIT_3D => X"A69B918576614C3A2C2424293649647E98B0C6D6DBDAD7D7D7D5D2D0CECDCDCC",
      INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFCEBD7C2B3B3C5DFF3FDF7E4CDB7AAA8AAAC",
      INIT_3F => X"BEBBB9B9BABFC7D1DAE0DFDAD1C6BDC0CCDDEFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_40 => X"503E312824232529314159718AA1B9CCD5D8DADCDBD8D4D0CFD0D1D1CFCBC7C2",
      INIT_41 => X"FFFFFFFFFFFFFFFFF9F9F5DFCAB8B0B7CAE1F1F8F4E6D3BFB0ABA8A396857362",
      INIT_42 => X"C8CACFD4D9DCDEDFDFDACFC9CBD5E4F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_43 => X"333C4042454E5F718395AABDCBD4DADFDFD9D3CECDCED0D3D3D2D0CECCCAC9C8",
      INIT_44 => X"FFFFFFFFF0F0EBD1BCAFAFBCCFDEE8EEEEE8DDCFC0B5AC9F8A7159443327252A",
      INIT_45 => X"D4D5D9E0E8E9DFD2C9C9D4E6F2F8FBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_46 => X"6B6C747D85909FB0BFCDD8DFDED8D1CBCBCDD0D3D5D7D8D8D8D8D7D6D5D4D4D4",
      INIT_47 => X"E3E3DDC1AFABB4C7D5DADDE1E6E9E7DFCFBFAD977B5D422D1F1C273A51646C6D",
      INIT_48 => X"EEF4ECDCCBC2C4D2E1EDF6FEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_49 => X"93949AA5B3C1CDD6D8D5D0CDCECFD1D4D7D9DADBDCDCDCDBD9D8D6D3D1D2D7E2",
      INIT_4A => X"ADB1C0D4DBDAD7D9E2ECF2EEDCC4A88968482E1D171F365578929FA09B969594",
      INIT_4B => X"CDC1BEC9D9E8F5FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD4D4CEB7",
      INIT_4C => X"A9B5C0CACED0D0D1D2D3D3D3D4D5D6D7D8D8D8D8D7D6D3D0CECED3DEEAF1EDDF",
      INIT_4D => X"DED9D3D5E0EFFAF8E3C4A17B583B261D20325178A0BFD0D2CCC3BBB2A79F9CA0",
      INIT_4E => X"D7E7F5FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCECEC9B7B2BAC9DA",
      INIT_4F => X"C3CACFD4D7D7D5D3D2D1D1D1D1D1D1D2D2D1CFCCCACACFD8E3E9E8DED0C4C0C8",
      INIT_50 => X"E1F2FFFEE7C49A714E352827334C719BC5E7FAFEF8EDE1D1BFAFA39FA2A9B3BC",
      INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCCCCC8BAB9C3D2E0E1DAD3D4",
      INIT_52 => X"DCDAD6D1CFCDCDCDCDCDCECFCFCFCDCBC9C9CDD5DDE3E3DDD3C8C3C7D3E2F1FD",
      INIT_53 => X"E8C3986F4E3B343A4C698DB6DEFEFFFFFFFFF9E7D3BFAEA3A0A2A7AFB8C4CFD8",
      INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7C7C4BBBFCBDCE8E7DDD4D3DFF1FFFF",
      INIT_55 => X"CCCBCBCCCDCDCECECECECDCBCACBCED5DBE0E0DCD7CFC6C5CAD5E4F4FFFFFFFF",
      INIT_56 => X"5849464E607B9CBFE2FEFFFFFFFFFAEBDBCABAADA5A1A2A7B2C0CDD8DDDAD5CF",
      INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFC1C1BEB8BECFE3F0EDE2D7D4DEEEFAF9E4C29A75",
      INIT_58 => X"CECECECECECECECDCDCED1D6DADDDDDBD9D3C8BFBDC2CFE3F3FBFDFDFFFFFFFF",
      INIT_59 => X"728AA7C6E5FEFFFFFFFFFBEFE3D5C6B8ADA5A2A5AFBDCDD8DCDAD3CDCAC9CACC",
      INIT_5A => X"FFFFFFFFFFFFFFFFBBBBB7B2BCD0E6F5F3E8DCD7DEEAF2F1DEC1A081695D5A62",
      INIT_5B => X"CFCFCFD0D0D1D3D7D9DBDAD9D9D6CBBAADA9B0C2D7E6F1F9FFFFFFFFFFFFFFFF",
      INIT_5C => X"D9EEFDFFFFFFFCF5EADED0C2B5AAA5A6B0BECEDADDDAD3CCC9C9CACDCFCFCFCF",
      INIT_5D => X"FFFFFFFFB7B7B3AEBAD0E8F9F8ECDFD9DCE3E8E6D7C1A891807573778395AAC2",
      INIT_5E => X"D0D1D3D6D8D9D8D8D9D7CCB7A2938D96A9BED0E1F2FAFDFEFEFFFFFFFFFFFFFF",
      INIT_5F => X"FEFFFDF7EEE3D6C9BCB3ADAEB7C5D3DEE0DDD6CFCBCACBCDCFCFCFCFCFCFCFD0",
      INIT_60 => X"B7B7B4AFBBD1EAFAF9EDDED7D7DBDFDDD1C2B1A1948B86888E9BABBCCFE1F0F9",
      INIT_61 => X"D8D9D7D6D7D4C8B39A8373738196ADC3D9E8F1F7FEFFFFFFFFFFFFFFFFFFFFFF",
      INIT_62 => X"EEE2D7CCC3BCB9BBC4D0DCE4E5E1DAD2CDCCCCCECFCFCFCFD0D0D0D1D1D2D3D5",
      INIT_63 => X"BFD4EDFBF9EBDBD2D2D5D8D7CFC5BAAEA398908C8E96A3B2C4D6E6F1F9FDFCF7",
      INIT_64 => X"D4D0C5B1987F6A636D8097AFC8DAE8F3FEFFFFFFFFFFFFFFFFFFFFFFBBBBB8B3",
      INIT_65 => X"C5C3C3C6CED7E0E6E7E3DDD6D1CFCFD0D0D0D0D0D0D0D0CFCFD0D1D4D7D8D7D5",
      INIT_66 => X"F5E7D8CFCED0D2D2CDC7C1B9B0A499918F939DABBBCCDCE8F1F6F7F1E7DBD1CA",
      INIT_67 => X"A6938071758194A9C0D3E3F1FDFFFFFFFFFFFFFFFFFFFFFFC2C2BFB9C1D4EAF8",
      INIT_68 => X"CFD5D9DDDDDCD8D5D3D1D1D0D0D0D0D0D0D0CFCECECECFD1D4D6D5D4D3D0C8B8",
      INIT_69 => X"CFCECFCECCCAC8C5BFB5AAA09B9BA1AAB6C3CED8DFE3E3DED5CBC4C0C0C3C6CA",
      INIT_6A => X"9C9EA5B1C2D3E3F1FEFFFFFFFFFFFFFFFFFFFFFFCCCCC8BDC0CEDFECECE2D7D0",
      INIT_6B => X"CECFD1D2D3D3D2D1D0D0CFCFCFCECDCCCBCBCBCDCFD0D1D2D4D4D0C9BFB5AA9E",
      INIT_6C => X"CCCDCECDCAC3BAB2ACABAEB4BBC1C5C8C9C9C5BEB6AFACAEB3BBC3C8CBCBCBCC",
      INIT_6D => X"C9D8E6F3FEFFFFFFFFFFFFFFFFFFFFFFD4D4CFC0BCC4D1E0E3E0D9D6D4D2D0CE",
      INIT_6E => X"D2D4D3D2D0D0CFCFCECDCBCAC9C8C8C8C9CBCDD0D4D8D9D9D8D5D0C7C0BBB9BD",
      INIT_6F => X"CFCBC7C2BEBCBEC0C3C2BFBBB6B0A9A19B97979CA6B1BBC1C1BDB9B8BBC1C7CD",
      INIT_70 => X"FEFFFFFFFFFFFFFFFFFFFFFFDCDCD8C4BAB9C2D1DADCDCDCDBD8D4D0CECFD0D0",
      INIT_71 => X"D2D2D1D1CFCECCCAC8C7C7C7C7C9CCD0D5DADEE1E4E6E4DCD2CAC6C8D3E0ECF6",
      INIT_72 => X"D0CCCAC8C5BEB6AFA7A098918C8A8C919AA5ADB2AFA8A2A1A7B1BDC8D1D5D5D4",
      INIT_73 => X"FFFFFFFFFFFFFFFFE7E7E2CAB7AFB0C0CED8DFE4E4DFD8D2D0D0D2D4D4D4D3D2",
      INIT_74 => X"D5D3D0CDCAC8C8C8CACCCFD3D6D9DBDBDCDCD8CEC7C4C6CEDCE9F2F8FEFFFFFF",
      INIT_75 => X"C0B5ACA6A19D98959494949596999A99958F8C8E99A7B8C7D4DBDCDBD9D9D8D7",
      INIT_76 => X"FFFFFFFFF2F2EDD5BFAEA8B0C2D3E0E9EAE4DBD3D0D0D2D4D6D9DCDEDDD8D1C9",
      INIT_77 => X"CDCBCACCD0D3D5D6D7D7D3CCC5BDB3A7A8B1C2D6EBF7FCFCFEFFFFFFFFFFFFFF",
      INIT_78 => X"A6A8A8A9ABACA9A2998F86807B797B8392A4B7CADAE3E5E4E2E2E1E0DDD9D5D1",
      INIT_79 => X"F9F9F5DFC9B6A9ADBCD0E2EDEEE7DBD1CDCCCED0D3D8DEE3E3DDD2C5B8ACA6A5",
      INIT_7A => X"D6DADBD9D7D2C9BAAC9D8E828EA8C6E4FEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_7B => X"C6C6C0B19E89776B66666D7B8CA0B4C7D8E2E5E4E3E4E3E2E0DCD8D4D0CDCED1",
      INIT_7C => X"D4C0B0ADBACEE1EEF0E8DCD2CDCCCDCFD2D7DEE3E3DBCCBBABA09EA4ADB6BCC2",
      INIT_7D => X"D3CBBFAE9C8B818497B5D4F0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFDFAE8",
      INIT_7E => X"A3876F5E585C64748495A6B8C7D0D3D3D3D5D6D6D4D4D3D1D0D0D1D6DBDDDCD8",
      INIT_7F => X"B6C8DBEBEFE9DDD3D0D0D2D4D6D9DDDFDBCFBBA6948B8F9DB0C2CFD8DDDCD1BD",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 3) => addra(11 downto 0),
      ADDRARDADDR(2 downto 0) => B"111",
      ADDRBWRADDR(15 downto 0) => B"0000000000000000",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
      DIADI(31 downto 8) => B"000000000000000000000000",
      DIADI(7 downto 0) => dina(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 0) => B"0000",
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
      DOADO(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7 downto 0),
      DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
      DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
      DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
      DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
      ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
      ENBWREN => '0',
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => ena,
      REGCEB => '0',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
      WEA(3) => wea(0),
      WEA(2) => wea(0),
      WEA(1) => wea(0),
      WEA(0) => wea(0),
      WEBWE(7 downto 0) => B"00000000"
    );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => addra(12),
      I1 => ena,
      I2 => addra(13),
      O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\ is
  port (
    DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\;

architecture STRUCTURE of \PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\ is
  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 0,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"9E9797A2B6CCE2F5FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCEFDECBB9B0",
      INIT_01 => X"575A6471808E9DAAB7BDC0C0C0C1C1C0C1C3C6C8CACDD2D7DCDEDBD5CEC4B6A7",
      INIT_02 => X"EFEADFD6D5D8DCDFDFDDDBD6CCBAA188746E7991AECADEEAEEEADEC8AC8D725F",
      INIT_03 => X"D8E6F0FAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF2E6D6C4B6B6C4D6E8",
      INIT_04 => X"86929EA7AFB3B3B2B1AFAEACABB0B9C0C6CCD3D8DBDBD7D0C8BEB1A8A6ACB8C7",
      INIT_05 => X"DBE1E7EBE8E1D7CBBAA2876D5B596A88ADCFE7F3F5EFE1CBB2957B6761646E7A",
      INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF6EFE3D1BFB7BECDE0EAE7DFD9",
      INIT_07 => X"B7B7B4AFAAA49F9B9CA4B2BFC9D2D9DBDAD5CFC7BFB7B1B1B8C4D3E4F1F8FBFD",
      INIT_08 => X"E9DDCEBDA9927B685D5F708EAFCDE2E9E8DFD1C1AE9A877A79818D99A3ABB1B5",
      INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFCFBF5E5CDBCB7BECDDBDEDCDBE0E7EDEE",
      INIT_0A => X"AB9E959295A2B7C9D7E1E6E3DBD2CBC7C4C3C3C8D1DCE8F5FEFFFFFFFFFFFFFF",
      INIT_0B => X"9D8E847E7E848FA0B2C0C8C7C1B7ADA7A29F9FA3AAB3BCC5CDD3D6D7D3CDC4B8",
      INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFEFFFFFFF6DFCABBB6BAC4CED5DCE5EBEEEBE3D4C2AF",
      INIT_0D => X"96A8C3D9EAF4F5EDDFD2CDCED2D7DCE3E9EEF4FAFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_0E => X"B2BABCBAB5AEA59A8F86818997A7B8C7D3DCE2E8EFF4F7F7F1E5D7C4AF9B908F",
      INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFDECD9C6B8B2B7C4D2DFEAEEEBE4D9C9B6A599949AA5",
      INIT_10 => X"F6FEFCEFE0D6D6DDE6EEF4FAFDFDFDFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_11 => X"BCA18874655C5B7291B2CDE1ECF3F7FAFFFFFFFFFCEDDCC7B09C9395A0B5D1E7",
      INIT_12 => X"FFFFFFFFFFFFFFF5E8D9C9BBB8BFCDDBE7E8E1D6CABBAB9D989EB3CDE5EEE7D4",
      INIT_13 => X"E4E1E5EEF5FAFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_14 => X"554B4E7099C1DEF0F8FBFDFEFFFFFFFEF0DFCEBDAEA3A1A9B6CAE0F0F9FCF7EE",
      INIT_15 => X"FFFFFFFBF6EFE4D3C8C5CBD4D8D6CCC0B5AA9F9899A5BFDDF6FFF5DEBF9F8067",
      INIT_16 => X"FCFDFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_17 => X"AAD0E9F7FDFFFFFEFCF7EEE0CDBEB6B3B5BBC3CFDBE9F2F7F6F3EFEDEBEDF2F8",
      INIT_18 => X"FDFCF5E9DCD5D2D2CEC5BAAFA5A09C9CA2B1C9E3F8FFF6E3C8AB8D735E525D80",
      INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
      INIT_1A => X"FBFCF9F2E8DBCBB9ABA8B0BFD1E2F0F9FEFFFBF5EFEBECEFF2F6FAFEFFFFFFFF",
      INIT_1B => X"ECE3DBD3C6B9AA9D9494979DA8BAD0E6F8FFF9EAD5BCA28B78717A97B9D8ECF7",
      INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6",
      INIT_1D => X"CCBDAEA3A1ADC0D8EEFFFFFFFFFCF2E9E6E9F1F7FBFDFFFFFFFFFFFFFFFFFFFF",
      INIT_1E => X"C6B3A08F83848991A0B4CAE0F2FBF7EAD7C2AE9F959298AAC0D6E4ECEFECE5DA",
      INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF7EFE5D9",
      INIT_20 => X"B7C7D6E2EBF0F1EDE7E2E0E1E6EEF8FEFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_21 => X"958D8B8F96A1B0BFCED7D8D0C4B9B1B0B1B3B5B8BEC4C9CCCBC6BFB6B0AAA9AC",
      INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFAF5EEE3D3C3B2A3",
      INIT_23 => X"D5D2D0D0D2D7DFE6EDF4FCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_24 => X"928F939CA6AFB3B1ACA9AEBAC8D2D4CABBAC9F97939191959EACBCCCDAE0DFDA",
      INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFCFAF6EFE4DAD1C6B8AAA098",
      INIT_26 => X"D9E6F1F6F9FAFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_27 => X"868A8F8F9095A4BCD5E7EAD9BA9476635E626E8198B2CDE1EBE8DCCCC0BEC3CD",
      INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFEFEFBF7F4F1EADECFC0B19F908683",
      INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2A => X"848B99B1CDE1E6D6B48A6652505A6C849CB4CADAE1DCD1C6C1C7D3E2F0FEFFFF",
      INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF0E2D2BFAB9D948E8A8684",
      INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_2D => X"B8C8CDC3AB8C73676975879BAAB7C0C8CDCECDCED2DCE6F0F8FFFFFFFFFFFFFF",
      INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F1E9DDCEC3BAB1A89E97939298A6",
      INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_30 => X"A89A908E94A0ADB9BFC1C2C4CAD2DAE1EAF2F8FBFDFFFFFFFFFFFFFFFFFFFFFF",
      INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFDFBF9F3EBE5DED7CDC1B7AEA6A2A5ADB5BAB5",
      INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_33 => X"B3BCC6CED1D1D0D1D9E3EDF5FDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFDF9F5EFE7DCD2C8BEB5B2B5B9BAB8B2ABA9AB",
      INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_36 => X"D1D1D0D1D9E3EDF5FDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_37 => X"FFFFFFFFFFFFFFFFFFFDF9F5EFE7DCD2C8BEB5B2B5B9BAB8B2ABA9ABB3BCC6CE",
      INIT_38 => X"00000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"00000",
      INIT_B => X"00000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"00000",
      SRVAL_B => X"00000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
        port map (
      ADDRARDADDR(13 downto 3) => addra(10 downto 0),
      ADDRARDADDR(2 downto 0) => B"000",
      ADDRBWRADDR(13 downto 0) => B"00000000000000",
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DIADI(15 downto 8) => B"00000000",
      DIADI(7 downto 0) => dina(7 downto 0),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(1 downto 0) => B"00",
      DIPBDIP(1 downto 0) => B"00",
      DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
      DOADO(7 downto 0) => DOADO(7 downto 0),
      DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
      DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
      DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\,
      DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
      ENARDEN => ena_array(0),
      ENBWREN => '0',
      REGCEAREGCE => ena,
      REGCEB => '0',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      WEA(1) => wea(0),
      WEA(0) => wea(0),
      WEBWE(3 downto 0) => B"0000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_prim_width is
  port (
    \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end PICTURE_R_ROM_blk_mem_gen_prim_width;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init
     port map (
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7 downto 0),
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized0\ is
  port (
    \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized0\;

architecture STRUCTURE of \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\
     port map (
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7 downto 0),
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized1\ is
  port (
    DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized1\;

architecture STRUCTURE of \PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\PICTURE_R_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\
     port map (
      DOADO(7 downto 0) => DOADO(7 downto 0),
      addra(10 downto 0) => addra(10 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      ena => ena,
      ena_array(0) => ena_array(0),
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_generic_cstr is
  port (
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end PICTURE_R_ROM_blk_mem_gen_generic_cstr;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_generic_cstr is
  signal ena_array : STD_LOGIC_VECTOR ( 4 to 4 );
  signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
  signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
  signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.PICTURE_R_ROM_bindec
     port map (
      addra(2 downto 0) => addra(13 downto 11),
      ena => ena,
      ena_array(0) => ena_array(4)
    );
\has_mux_a.A\: entity work.PICTURE_R_ROM_blk_mem_gen_mux
     port map (
      DOADO(7) => \ramloop[2].ram.r_n_0\,
      DOADO(6) => \ramloop[2].ram.r_n_1\,
      DOADO(5) => \ramloop[2].ram.r_n_2\,
      DOADO(4) => \ramloop[2].ram.r_n_3\,
      DOADO(3) => \ramloop[2].ram.r_n_4\,
      DOADO(2) => \ramloop[2].ram.r_n_5\,
      DOADO(1) => \ramloop[2].ram.r_n_6\,
      DOADO(0) => \ramloop[2].ram.r_n_7\,
      addra(2 downto 0) => addra(13 downto 11),
      clka => clka,
      douta(7 downto 0) => douta(7 downto 0),
      \douta[7]\(7) => \ramloop[1].ram.r_n_0\,
      \douta[7]\(6) => \ramloop[1].ram.r_n_1\,
      \douta[7]\(5) => \ramloop[1].ram.r_n_2\,
      \douta[7]\(4) => \ramloop[1].ram.r_n_3\,
      \douta[7]\(3) => \ramloop[1].ram.r_n_4\,
      \douta[7]\(2) => \ramloop[1].ram.r_n_5\,
      \douta[7]\(1) => \ramloop[1].ram.r_n_6\,
      \douta[7]\(0) => \ramloop[1].ram.r_n_7\,
      \douta[7]_0\(7 downto 0) => ram_douta(7 downto 0),
      ena => ena
    );
\ramloop[0].ram.r\: entity work.PICTURE_R_ROM_blk_mem_gen_prim_width
     port map (
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7 downto 0) => ram_douta(7 downto 0),
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
\ramloop[1].ram.r\: entity work.\PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized0\
     port map (
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
      \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
\ramloop[2].ram.r\: entity work.\PICTURE_R_ROM_blk_mem_gen_prim_width__parameterized1\
     port map (
      DOADO(7) => \ramloop[2].ram.r_n_0\,
      DOADO(6) => \ramloop[2].ram.r_n_1\,
      DOADO(5) => \ramloop[2].ram.r_n_2\,
      DOADO(4) => \ramloop[2].ram.r_n_3\,
      DOADO(3) => \ramloop[2].ram.r_n_4\,
      DOADO(2) => \ramloop[2].ram.r_n_5\,
      DOADO(1) => \ramloop[2].ram.r_n_6\,
      DOADO(0) => \ramloop[2].ram.r_n_7\,
      addra(10 downto 0) => addra(10 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      ena => ena,
      ena_array(0) => ena_array(4),
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_top is
  port (
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_top : entity is "blk_mem_gen_top";
end PICTURE_R_ROM_blk_mem_gen_top;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_top is
begin
\valid.cstr\: entity work.PICTURE_R_ROM_blk_mem_gen_generic_cstr
     port map (
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      douta(7 downto 0) => douta(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_v8_4_2_synth is
  port (
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    wea : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_v8_4_2_synth : entity is "blk_mem_gen_v8_4_2_synth";
end PICTURE_R_ROM_blk_mem_gen_v8_4_2_synth;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_v8_4_2_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.PICTURE_R_ROM_blk_mem_gen_top
     port map (
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      douta(7 downto 0) => douta(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM_blk_mem_gen_v8_4_2 is
  port (
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    eccpipece : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC;
    rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
    sleep : in STD_LOGIC;
    deepsleep : in STD_LOGIC;
    shutdown : in STD_LOGIC;
    rsta_busy : out STD_LOGIC;
    rstb_busy : out STD_LOGIC;
    s_aclk : in STD_LOGIC;
    s_aresetn : in STD_LOGIC;
    s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awvalid : in STD_LOGIC;
    s_axi_awready : out STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wlast : in STD_LOGIC;
    s_axi_wvalid : in STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_bready : in STD_LOGIC;
    s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_arvalid : in STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    s_axi_rready : in STD_LOGIC;
    s_axi_injectsbiterr : in STD_LOGIC;
    s_axi_injectdbiterr : in STD_LOGIC;
    s_axi_sbiterr : out STD_LOGIC;
    s_axi_dbiterr : out STD_LOGIC;
    s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 14;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 14;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "Estimated Power for IP     :     2.319445 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "spartan7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "PICTURE_R_ROM.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "PICTURE_R_ROM.mif";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 10000;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 10000;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 10000;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 10000;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "spartan7";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "blk_mem_gen_v8_4_2";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of PICTURE_R_ROM_blk_mem_gen_v8_4_2 : entity is "yes";
end PICTURE_R_ROM_blk_mem_gen_v8_4_2;

architecture STRUCTURE of PICTURE_R_ROM_blk_mem_gen_v8_4_2 is
  signal \<const0>\ : STD_LOGIC;
begin
  dbiterr <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  rdaddrecc(13) <= \<const0>\;
  rdaddrecc(12) <= \<const0>\;
  rdaddrecc(11) <= \<const0>\;
  rdaddrecc(10) <= \<const0>\;
  rdaddrecc(9) <= \<const0>\;
  rdaddrecc(8) <= \<const0>\;
  rdaddrecc(7) <= \<const0>\;
  rdaddrecc(6) <= \<const0>\;
  rdaddrecc(5) <= \<const0>\;
  rdaddrecc(4) <= \<const0>\;
  rdaddrecc(3) <= \<const0>\;
  rdaddrecc(2) <= \<const0>\;
  rdaddrecc(1) <= \<const0>\;
  rdaddrecc(0) <= \<const0>\;
  rsta_busy <= \<const0>\;
  rstb_busy <= \<const0>\;
  s_axi_arready <= \<const0>\;
  s_axi_awready <= \<const0>\;
  s_axi_bid(3) <= \<const0>\;
  s_axi_bid(2) <= \<const0>\;
  s_axi_bid(1) <= \<const0>\;
  s_axi_bid(0) <= \<const0>\;
  s_axi_bresp(1) <= \<const0>\;
  s_axi_bresp(0) <= \<const0>\;
  s_axi_bvalid <= \<const0>\;
  s_axi_dbiterr <= \<const0>\;
  s_axi_rdaddrecc(13) <= \<const0>\;
  s_axi_rdaddrecc(12) <= \<const0>\;
  s_axi_rdaddrecc(11) <= \<const0>\;
  s_axi_rdaddrecc(10) <= \<const0>\;
  s_axi_rdaddrecc(9) <= \<const0>\;
  s_axi_rdaddrecc(8) <= \<const0>\;
  s_axi_rdaddrecc(7) <= \<const0>\;
  s_axi_rdaddrecc(6) <= \<const0>\;
  s_axi_rdaddrecc(5) <= \<const0>\;
  s_axi_rdaddrecc(4) <= \<const0>\;
  s_axi_rdaddrecc(3) <= \<const0>\;
  s_axi_rdaddrecc(2) <= \<const0>\;
  s_axi_rdaddrecc(1) <= \<const0>\;
  s_axi_rdaddrecc(0) <= \<const0>\;
  s_axi_rdata(7) <= \<const0>\;
  s_axi_rdata(6) <= \<const0>\;
  s_axi_rdata(5) <= \<const0>\;
  s_axi_rdata(4) <= \<const0>\;
  s_axi_rdata(3) <= \<const0>\;
  s_axi_rdata(2) <= \<const0>\;
  s_axi_rdata(1) <= \<const0>\;
  s_axi_rdata(0) <= \<const0>\;
  s_axi_rid(3) <= \<const0>\;
  s_axi_rid(2) <= \<const0>\;
  s_axi_rid(1) <= \<const0>\;
  s_axi_rid(0) <= \<const0>\;
  s_axi_rlast <= \<const0>\;
  s_axi_rresp(1) <= \<const0>\;
  s_axi_rresp(0) <= \<const0>\;
  s_axi_rvalid <= \<const0>\;
  s_axi_sbiterr <= \<const0>\;
  s_axi_wready <= \<const0>\;
  sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst_blk_mem_gen: entity work.PICTURE_R_ROM_blk_mem_gen_v8_4_2_synth
     port map (
      addra(13 downto 0) => addra(13 downto 0),
      clka => clka,
      dina(7 downto 0) => dina(7 downto 0),
      douta(7 downto 0) => douta(7 downto 0),
      ena => ena,
      wea(0) => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PICTURE_R_ROM is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of PICTURE_R_ROM : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of PICTURE_R_ROM : entity is "PICTURE_R_ROM,blk_mem_gen_v8_4_2,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of PICTURE_R_ROM : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of PICTURE_R_ROM : entity is "blk_mem_gen_v8_4_2,Vivado 2018.3";
end PICTURE_R_ROM;

architecture STRUCTURE of PICTURE_R_ROM is
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 14;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 14;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.319445 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "spartan7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 0;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "PICTURE_R_ROM.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "PICTURE_R_ROM.mif";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 1;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 0;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 10000;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 10000;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 10000;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 10000;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "spartan7";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.PICTURE_R_ROM_blk_mem_gen_v8_4_2
     port map (
      addra(13 downto 0) => addra(13 downto 0),
      addrb(13 downto 0) => B"00000000000000",
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => douta(7 downto 0),
      doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => '0',
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
      s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
